1. Field of Invention
The present invention relates to burn-in testing. More particularly, the present invention relates to a method of operation for shortening burn-in time.
2. Description of Related Art
To assess the quality of a semiconductor device such as an integrated circuit (IC), burn-in testing is normally carried out after the completion of wafer fabrication. In general, the burn-in testing is conducted after the semiconductor is packaged. During burn-in testing, if one or two lines in the column address, row address or certain bit location have defects, nothing can be done to repair those defective items. Those units either have to be scrapped or have to be sold as an inferior product at a reduced price. Hence, product yield is lowered.
Conventionally, a burn-in testing includes sequentially conducting a single read and a single write operation on a memory cell to detect any errors. However, this mode of burn-in testing is not only time consuming, but also incurs high testing cost.
An example is given with reference to FIG. 1. FIG. 1 is a block diagram showing a conventional address decoder. For a memory chip such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), each of these units comprises an address decoder 10. Furthermore, this address decoder 10 has at least three address input terminals A2, A1 and A0. Table 1 below shows the logic states of various output lines according to the input states for a conventional address decoder. During a burn-in testing, if the input values to terminals (A2,A1,A0) is (0,0,0), the word line address X0 will be selected by the internal circuit of the address decoder 10. In other words, the output from X0 is a logic "1", while the outputs from X1 to X7 are logic "0". With appropriate address selection, functional tests such as the execution of a read and a write operation can be carried out with respect to the word line address X0. Then, when the testing of word line address X0 is over, logic values of (0,0,1) can be input to the input terminals (A2,A1,A0). Again, after passing through the internal circuit of the address decoder 10, the word line address X1 will be selected. In other words, the output from X1 is logic "1", while the outputs from X0 and X2 to X7 are logic "0". With address selected, read and write functional operations can be carried out with respect to the word line address X1. Similarly, when the testing of word line address X1 is over, logic values of (0,1,0) to (1,1,1) can be input to the input terminals (A2,A1,A0) to select the corresponding word line addresses X2 to X7 one after the other. Therefore, read and write operations with respect to these other word line addresses X2 to X7 can then be executed one by one. Obviously, there is no restriction to how the word line addresses are selected for carrying out the burn-in testing. For example, for a three bits input address decoder, as long as read and write operations for all the word line addresses obtained by decoding the inputs from (0,0,0) to (1,1,1) are checked, the burn-in operation is considered adequate. However, finishing these sequences of testing operations require a long time and adds to the cost of production.
TABLE 1 ______________________________________ A2 A1 A0 X7 X6 X5 X4 X3 X2 X1 X0 ______________________________________ 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 ______________________________________
In light of the foregoing, there is a need to shorten the burn-in testing time.